The present invention relates to circuits used to program an electrically blowable fuse, especially integrated circuits having such function.
Fuses are used to support memories of integrated circuits or “chips” such as stand-alone memory chips and memory macros of chips by storing information regarding the allocation of redundancy elements within such memories. Fuses are also used to store permanent settings within chips, such as chips which contain identification codes and the like. When used to support a memory macro of an integrated circuit memory, the macro is tested to identify any failing locations of the macro. A repair solution is then generated for the pattern of failing locations utilizing redundancy elements available on the chip to replace corresponding failing elements. A block or array of fuses is then programmed, i.e., controllably blown, as a way of storing information regarding the repair solution. Thereafter, whenever an attempt is made to access the failing memory locations, the access operation will be detoured to a set of redundancy addresses stored in the fuse array.
While some types of fuses are programmed by applying intense heat directly to the fuse, e.g. via laser irradiation, other types of fuses are electrically programmable or “blowable” by passing a high current through the fuse, e.g., as by applying a higher than normal electric potential across the fuse. Application of such high current causes electromigration of the material of the fuse, causing the resistance of the fuse to increase. The state of the fuse, i.e., the condition of whether the fuse has been programmed or not, can be determined by applying a low electric potential across the fuse and measuring the amount of current that the fuse conducts.
For example, FIG. 1 illustrates a prior art circuit 10 used to program an electrically blowable fuse, and, in addition, to determine whether the fuse is in a programmed state or an unprogrammed state. As shown in FIG. 1, the circuit 10 includes a NAND gate N0 to which fuse logic enable signals FENABLE1 and FENABLE2 are input, an inverter I1 coupled to the output of the NAND gate N0, the electrically blowable fuse F0, a transistor N1 used during an operation to program or “set” the fuse F0, as well as during an operation to determine the state of the fuse F0. Determination of the programming state of the fuse F0 is performed by a resistance measuring circuit 12 based on the output FOUT taken at the drain of transistor N1. Typically, the resistance of the fuse F0 in the unprogrammed state is about 100 ohms to about 200 ohms.
To program or “set” the fuse, inputs FENABLE1 and FENABLE2 are set to “1”, i.e., to the high logic level at the upper power supply voltage level Vdd of about 1.0 to 1.5 V, causing the output of the NAND gate N0 to fall to “0” or low. This output from NAND gate N0 is then inverted to the logic high level by inverter I1 and applied to the gate of transistor N1, in turn causing transistor N1 to conduct. To program the fuse, FSOURCE is set to a voltage, e.g., 3.3 V which is higher than an ordinary power supply voltage level of Vdd. The 3.3 V potential is applied across the stack including the fuse F0 and transistor N1. At such time, the input to the resistance measuring circuit 12 is placed in a high impedance or “off” state to prevent current flow thereto. Since FSOURCE is capable of sourcing a high programming current, e.g., about 10 mA, such high current flows through fuse F0 and causes electromigration therein sufficient to change the resistance of the fuse from the minimal 100 to 200 ohm initial resistance to a much higher value such as 5 kilo-ohms. After maintaining the high current long enough to program the fuse, the potential at FSOURCE is lowered again to ground.
At other times, the state of the fuse of being in the programmed state or not is determined by again setting the FENABLE1 and FENABLE2 inputs to the logic high levels, which drives the output of NAND gate N0 to low, in turn causing inverter I1 to drive the gate of transistor N1 to high, causing transistor N1 to conduct. At this time, the potential at FSOURCE is raised from logic level low (usually at ground) to a relatively low voltage permitting conduction, e.g., about 100 mV. FSOURCE is held at such potential for about 100 μs to allow the resistance measuring circuit 12 to determine the state of the fuse. During such operation, circuit 12 measures the current sourced from the FSOURCE node and determines the resistance of the electrically blowable fuse F0. Under the applied biasing conditions, with the voltage applied between the gate and the source of N1 at Vdd (about 1.0 to 1.5 V), and the voltage applied by FSOURCE between the drain and the source of about 100 mV, transistor N1 operates in a linear mode. Unfortunately, the measurement operation is not robust against possible variations in the manufacturing process and operating conditions of the chip, leading to possibly inaccurate measurements which potentially affect the ultimate determination of the state of the fuse. Measurement under such biasing conditions potentially introduces error because a slight deviation in either the voltages applied to the gate of transistor N1 or the drain will cause the amount of current conducted by transistor N1 to vary significantly.